1. Field Of The Invention
The present invention relates to CMOS logic circuits. More particularly, the present invention relates to clocked register logic circuits.
2. The Prior Art
Numerous sequential logic circuits are in common use. Such circuits employ various clocking schemes. Some known register circuits employ single phase clocks. Other known register circuits, such as the circuit disclosed and claimed in U.S. Pat. No. 4,716,312 to Mead et al. employ two-phase clocks.
The various clocking schemes employed for use in CMOS register circuits offer various tradeoffs. In one single phase clock scheme, a single phase clock and its complement are distributed and are used to control either transmission gates or transistors controlling power to P-channel and N-channel transistor switching networks. Proper operation of such circuits requires that the logic delay of the stage exceed the clock skew between the two clock lines. An approach having relaxed clocking requirements utilizes a two-phase clock in which two different phase clock signals and their complements are distributed. The reduced risk of this circuit is achieved at the expense of more complex clock waveform generation. Another popular form of register used in gate-level designs employs a single phase distributed clock which is locally inverted at master-slave elements. While this approach results in a low risk circuit, it does so at the expense of requiring at least ten devices per minimum storage element.